1. Field
Exemplary embodiments of the present invention relate to an integrated circuit system.
2. Description of the Related Art
In an integrated circuit system field, a packaging technology of a semiconductor element has been continuously developed with demand for miniaturization and high capacity. There have been developed various technologies for a stacked semiconductor package capable of satisfying mounting efficiency as well as miniaturization and high capacity.
The stacked semiconductor package may be fabricated using a method, in which individual semiconductor chips are stacked upon one another and the stacked chips are packaged at a time, or a method in which individually packaged semiconductor chips are stacked upon one another. In the stacked semiconductor package, the individual semiconductor chips are electrically connected to one another through metal wires, through-silicon vias (TSVs) and the like.
However, in the conventional stacked semiconductor package using metal wires, since electrical signal exchange is performed through the metal wires, speed is low and a large number of wires are used, resulting in the deterioration of electrical characteristics. Furthermore, an additional area is assigned in a substrate in order to form the metal wires, resulting in an increase in the size of the package. Moreover, a cap for wire bonding is provided among semiconductor chips, resulting in an increase in the height of the package.
In this regard, there has been proposed a stacked semiconductor package using a through-silicon via (TSV). In general, the stacked semiconductor package is fabricated by forming via holes passing through semiconductor chips, forming through electrodes (through-silicon vias) by filling the via holes with conductive materials, and electrically connecting upper semiconductor chips to lower semiconductor chips through the through electrodes.
Meanwhile, in order to operate a specific chip in the stacked semiconductor package, IDs are to be assigned to a plurality of semiconductor chips included in the stacked semiconductor package. When the plurality of semiconductor chips are formed using processes different from one another or include circuits different from one another (that is, when the plurality of semiconductor chips have structures different from one another), it is easy to assign IDs to the plurality of semiconductor chips using different structures of the plurality of semiconductor chips. However, it results in a reduction of the product yield and an increase in the fabrication cost to form the plurality of semiconductor chips using the processes different from one another and to package the plurality of semiconductor chips.
Therefore, in order to increase the product yield and reduce the fabrication cost, it is advantageous that semiconductor chips including substantially the same circuits formed using substantially the same processes are stacked upon one another. However, when substantially the same semiconductor chips are stacked upon one another, a method for assigning an ID to each semiconductor chip may be difficult. According to a method for assigning IDs to a plurality of the same semiconductor chips, a fuse circuit included in each semiconductor chip may be programmed, or different ID signals may be applied to the semiconductor chips from an exterior. In the former case, since it may be inconvenient to differently program the fuse circuits of the semiconductor chips one by one. In the latter case, in order to apply different ID signals to the semiconductor chips, different bondings are to be provided for the semiconductor chips.